Digital Comparator Explained: Equality and Magnitude

Derive equality and magnitude comparators, cascade 4-bit blocks, distinguish signed from unsigned ordering, and verify greater/equal/less outputs.

Denny

May 7, 20267 min read

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TL;DR: Equality is a reduction AND of bitwise XNOR results. Unsigned magnitude is decided by the most significant position where A and B differ. Signed magnitude needs a different interpretation of the sign bit or subtraction flags. A comparator is correct only when width, signedness, output polarity, and cascade inputs are all defined.

A comparator converts two bit vectors into a relationship:

A < B, A = B, or A > B

That sounds unambiguous until the same bits are interpreted differently. In four bits, 1000 is 8 unsigned but -8 in two’s complement. Compared with 0111, it is greater under unsigned interpretation and less under signed interpretation.

This guide builds equality first, derives an unsigned magnitude network, then shows how signed comparison and block cascading change the design.

Define the Contract

For two valid $n$ -bit inputs A and B, a three-output magnitude comparator commonly produces:

G: A is greater than B;
E: A equals B;
L: A is less than B.

Under a valid two-valued input model:

G+E+L=1

and no two outputs are high together. That one-hot relation depends on a complete implementation and valid logic levels. An enable input, active-low interface, unknown simulation values, or incorrectly initialized cascade inputs can change the visible behavior.

Equality does not depend on signedness: the bit vectors either match or they do not. Greater-than and less-than do.

Equality from XNOR

For one position:

E_i=A_i\odot B_i=\overline{A_i\oplus B_i}

$E_i=1$ when the two bits match. Entire words are equal only when all positions match:

E=\bigwedge_{i=0}^{n-1}E_i

For four bits:

E=(A_3\odot B_3)(A_2\odot B_2)(A_1\odot B_1)(A_0\odot B_0)

The direct schematic uses four XNOR gates followed by an AND reduction.

It is tempting to call that “two gate delays regardless of width.” That is only a Boolean-level drawing with unbounded fan-in. Physical implementations may build the reduction as a balanced tree, factor it into compound cells, or map it into FPGA lookup tables. With two-input AND gates, the reduction depth grows approximately as $\lceil\log_2 n\rceil$ when balanced.

Unsigned Magnitude: Highest Difference Wins

For each bit define:

G_i=A_i\overline{B_i}

L_i=\overline{A_i}B_i

E_i=A_i\odot B_i

At the most significant differing position, 1 in A and 0 in B means A is greater; the opposite means A is less. Lower positions matter only if every higher position matches.

For four-bit unsigned values:

\begin{aligned} G={}&G_3 +E_3G_2 +E_3E_2G_1 +E_3E_2E_1G_0 \end{aligned}

\begin{aligned} L={}&L_3 +E_3L_2 +E_3E_2L_1 +E_3E_2E_1L_0 \end{aligned}

E=E_3E_2E_1E_0

Each G term says “all higher bits tie and A wins here.” Each L term says the symmetric case.

Worked unsigned example

Compare:

A = 0110 (6)
B = 0101 (5)

Bits 3 and 2 match. At bit 1, A has 1 and B has 0, so $G_1=1$ . Bit 0 is irrelevant because a more significant difference already exists:

G=1, E=0, L=0

This is a priority function, but priority runs from the most significant data bit toward the least significant bit.

A Recursive Comparator Cell

Instead of expanding a long sum of products, combine groups hierarchically. Suppose H describes a high-order group and Lw describes a low-order group:

G_{\text{all}}=G_H\lor(E_H\land G_{Lw})

E_{\text{all}}=E_H\land E_{Lw}

L_{\text{all}}=L_H\lor(E_H\land L_{Lw})

The high group decides unless it is equal; only then does the low group pass through. This associative-style combine can form a linear cascade or a balanced hierarchy.

The equations explain the expansion inputs on a 4-bit magnitude-comparator IC. The block needs a lower-order G/E/L result in case its local four bits are tied.

Cascading SN74LS85 Blocks

The SN74LS85 compares two 4-bit straight-binary or 8-4-2-1 BCD words and exposes three expansion inputs plus three relationship outputs.

For an eight-bit comparison:

The low-order device compares bits 3:0.
Initialize its expansion relation to equal: G_in=0, E_in=1, L_in=0.
Connect its G/E/L outputs to the matching expansion inputs of the high-order device.
The high-order device compares bits 7:4 and produces the final result.

If the high halves differ, that local decision overrides the low input. If the high halves match, the low-order relation propagates.

Follow the exact data sheet for pin polarity, fan-out, voltage, and timing. The logical recursion does not substitute for electrical design.

Signed Two’s-Complement Comparison

Equality uses the same XNOR network for signed and unsigned values. Ordering differs.

Method 1: Interpret the sign bit separately

Let $s_A=A_{n-1}$ and $s_B=B_{n-1}$ .

If $s_A\ne s_B$ , the operand with sign bit 1 is less.
If the signs match, ordinary lexicographic comparison of the remaining relationship gives the correct order.

A convenient hardware transformation is to invert each operand’s MSB before feeding an unsigned comparator:

A'=A\oplus 2^{n-1}

B'=B\oplus 2^{n-1}

Flipping the sign bit biases two’s-complement ordering into unsigned ordering. For four bits:

signed -8 = 1000  → biased 0000
signed -1 = 1111  → biased 0111
signed  0 = 0000  → biased 1000
signed +7 = 0111  → biased 1111

The biased values now rise in the same order as the signed numbers.

Method 2: Subtract and interpret flags

If an ALU computes $R=A-B$ :

E is Z;
signed L is $N\oplus V$ ;
signed G is $\overline Z\land\overline{N\oplus V}$ .

Unsigned less-than depends on the subtraction carry convention. DigiSim’s ALUs expose a borrow flag after SUB, so unsigned L is C. A custom adder/subtractor exposing raw carry-out instead uses $\overline C$ , because raw carry 1 means no borrow. The CPU flags guide derives both conventions.

Do not use N alone for signed less-than. A signed overflow can invert the stored result’s apparent sign.

Example with opposite interpretations

A = 1000
B = 0111

Unsigned:

8 > 7

Signed two’s complement:

-8 < +7

A comparator labeled only “A>B” is underspecified until signedness is known.

Timing and Implementation Choices

A linear priority chain has depth proportional to width. A balanced group-combine network can reduce logical depth. Synthesis may use:

wide or compound gates;
prefix-like equality/greater combines;
subtraction hardware already present in an ALU;
FPGA carry-chain or lookup-table resources;
early-out structures for selected use cases.

No topology is universally fastest. A dedicated comparator may avoid waiting for an arithmetic result in one design, while reusing an adder may save area in another. Modern processors also distribute comparisons among branch, address-generation, vector, and other execution logic rather than implementing one monolithic comparator.

The timed path includes source clock-to-Q, input selection, comparator logic, routing, destination setup, and clock effects. Gate count alone does not establish maximum frequency.

Practical Uses

Exact address match

An equality comparator can generate a chip-select when an address equals a fixed value. For an aligned power-of-two region, compare only the upper address bits and treat lower bits as the offset. Arbitrary ranges may instead use inequalities or factored decode logic.

Bus correctness requires more than equality: enables, access type, privilege, and mutually exclusive ownership may also qualify the select.

Threshold and window checks

Control logic can test:

LOW\le X\le HIGH

with two magnitude comparisons. Pay attention to inclusive versus exclusive endpoints and whether X is signed.

Min/max and compare–select

A magnitude result can drive multiplexers:

min = (A < B) ? A : B
max = (A < B) ? B : A

The tie policy matters when each value carries metadata or when stable ordering is required.

Sorting networks

A compare–exchange cell combines one comparator with data-routing multiplexers. Fixed networks compose these cells in stages. Their latency depends on both comparator depth and the number of compare–exchange stages, not just the number of cells.

Build and Verify It in DigiSim

Use the comparator component as a reference, then construct the equations from gates:

Build four $E_i$ signals with XNOR.
Reduce them to E.
Build $G_i$ and $L_i$ for each position.
combine them from MSB to LSB.
Assert that exactly one of G/E/L is high for every valid input pair.
Add an MSB-bias option to switch between unsigned and signed comparison.

Exhaustive testing is practical at four bits: evaluate all $16\times16=256$ pairs.

For each pair, check:

E equals bit-vector equality;
unsigned G/L matches integers 0–15;
signed G/L matches integers -8–7;
swapping A and B swaps G and L but preserves E;
G, E, and L are mutually exclusive and collectively exhaustive.

Then cascade two four-bit blocks and target boundary pairs such as 0x0F/0x10, 0x7F/0x80, and equal high halves with different low halves.

A functional simulator establishes the Boolean relation. It does not establish physical propagation delay, electrical compatibility, or timing closure in the final technology.

Reference

Texas Instruments SN74LS85 4-bit magnitude comparator product page and data sheet