Digital Comparator Explained: Equality and Magnitude

TL;DR: A digital comparator is a combinational circuit that compares two N-bit binary numbers and outputs whether they are equal, or which one is larger. An equality comparator is built from a bank of bitwise XNOR gates fed into a single AND gate. A magnitude comparator adds priority logic that walks from the most significant bit downward, declaring A > B as soon as the highest differing bit is found.

The digital comparator is the answer to two questions every CPU and controller asks constantly: “are these two values the same?” and “which one is larger?” Memory address decoders use equality comparators to recognize their assigned address. Sorting networks use magnitude comparators to swap values into order. ALUs use comparators (or repurpose subtraction with flag interpretation) to drive every conditional branch instruction. The circuit itself reduces to a remarkably small amount of gate logic — and once the structure is clear, it scales cleanly from 1 bit to 64.

What is a digital comparator?

A digital comparator is a combinational circuit with two N-bit input buses, A and B, and one or more output flags that summarize the relationship between them. Two flavors exist:

• Equality comparator — single output: A = B (1) or A ≠ B (0).
• Magnitude comparator — three outputs: A > B, A = B, A < B. Exactly one is high at any time, so the three outputs together form a one-hot encoding of the relationship.

A magnitude comparator is a strict superset of an equality comparator: ignore the A>B and A<B outputs, and what remains is the equality answer. In simulator form, the parent block lives at /docs/COMPARATOR, with the wider variant at /docs/COMPARATOR_8BIT.

Equality from XNOR and AND

The 1-bit equality test is exactly the XNOR truth table:

For multi-bit equality, two numbers are equal when every bit position matches. The construction is one XNOR per bit, then a single multi-input AND that combines them:

$EQ = \prod_{i=0}^{N-1} (A_i \odot B_i)$

For 4-bit operands, that is four XNORs and one 4-input AND — five gates total. For 8-bit, eight XNORs and one 8-input AND. The propagation delay is two gate levels regardless of width, making equality the fastest comparison primitive available. The XNOR’s role as the equality gate is covered in The XNOR Gate: Champion of Equality in Digital Logic, and the multi-input AND that combines them is from the AND gate family.

A 1-bit cell looks like:

A ──┐
    XNOR ── (matches at this bit)
B ──┘

A 4-bit equality circuit:

A0,B0 ─► XNOR ─┐
A1,B1 ─► XNOR ─┤
A2,B2 ─► XNOR ─┤── 4-input AND ── A = B
A3,B3 ─► XNOR ─┘

Magnitude: walking down from the MSB

Magnitude comparison cannot be done bit-by-bit independently because lower-order bits only matter when the higher-order bits are tied. The standard approach scans from the most significant bit downward and produces a verdict at the first bit where A and B differ.

For 1-bit operands, the magnitude truth table is:

The Boolean equations:

• $G_0 = A \cdot \overline{B}$ (greater)
• $E_0 = A \odot B$ (equal — XNOR)
• $L_0 = \overline{A} \cdot B$ (less)

For 2 bits the equations chain through the higher bit:

• $G = G_1 + E_1 \cdot G_0$ — A > B at bit 1, or bits agree at 1 and A > B at 0
• $L = L_1 + E_1 \cdot L_0$ — symmetric
• $E = E_1 \cdot E_0$ — both bits agree

The pattern generalizes. For an N-bit comparator:

$G = G_{N-1} + E_{N-1} \cdot G_{N-2} + E_{N-1} \cdot E_{N-2} \cdot G_{N-3} + \ldots$

Each term contributes a “tie at all higher bits, A wins at this bit” path. Exactly one term can be 1 in any given input combination, because the leftmost differing bit decides everything.

Building a 4-bit magnitude comparator

A practical 4-bit magnitude comparator implements the chained equations above. The 7485 IC, introduced in 1972 and still in use as a teaching block, was the canonical 4-bit magnitude comparator. It exposes:

• 4 bits each of A and B inputs
• Three cascade inputs: A>B-in, A=B-in, A<B-in
• Three outputs: A>B, A=B, A<B

The cascade inputs implement the chaining: when feeding two 7485s in series, the lower-order chip’s three outputs drive the higher-order chip’s cascade inputs. Each chip then resolves its 4 bits and either declares a winner or, if all 4 of its bits are tied, defers to the cascade input from the lower chip.

This is exactly the same technique used by carry-propagate logic in a ripple-carry adder, and for the same reason: comparison and addition both require information to flow from least to most significant in the worst case. For the addition counterpart, see Mastering Binary Addition: Building a 4-Bit Ripple-Carry Adder.

Cascading to 8 bits and beyond

Two 4-bit comparators chain into an 8-bit comparator. The high-half chip handles bits 4-7. The low-half chip handles bits 0-3 and feeds its three outputs into the high-half chip’s cascade inputs. The high half decides the answer if any of its four bits differ; otherwise the low half’s verdict propagates through.

In one equation:

$G_{8} = G_H + E_H \cdot G_L$

$E_{8} = E_H \cdot E_L$

$L_{8} = L_H + E_H \cdot L_L$

This recursion stacks indefinitely. Four 4-bit chips compare 16-bit numbers. Eight chips compare 32-bit numbers. The propagation delay grows linearly with the number of stages — and that linear delay is why modern wide comparators do not actually use this naive cascade; they use parallel-prefix techniques (Brent-Kung or Kogge-Stone) that reduce the depth to logarithmic. The functional behavior is identical, only the timing differs. For an 8-bit pre-built block, see /docs/COMPARATOR_8BIT.

Use case 1: address decoders

Memory-mapped I/O assigns a fixed address (or address range) to each peripheral. When the CPU drives an address onto the address bus, every peripheral compares the bus value against its own assigned address. Whichever peripheral matches asserts its chip-select and responds; the others stay silent.

For exact-match decoding, an equality comparator is enough. For range matching (e.g., “addresses 0x4000 through 0x4FFF map to UART”), the upper bits of the address are compared for equality and the lower bits are ignored — which is just a narrower equality comparator. The MAR and address-decode network in a textbook CPU is a forest of small equality comparators, one per peripheral.

Use case 2: ALU flag generation

Inside an ALU, the comparator is sometimes a dedicated block and sometimes folded into the subtractor. The folded approach uses the existing adder/subtractor: compute A − B, then read the Z flag (A = B), the N XOR V combination (A < B for signed values), and the C flag (A < B for unsigned values).

A dedicated comparator runs in parallel with the adder and produces its outputs in shallower depth (two to three gate levels for equality, $O(\log N)$ for magnitude with parallel-prefix logic, versus the $O(N)$ ripple delay of a basic adder). High-performance CPUs include the dedicated comparator to enable single-cycle CMP-and-branch instructions; lower-area designs reuse the subtractor and accept the longer critical path. The full ALU picture, with the comparator as one of several parallel blocks feeding the output multiplexer, is in How an ALU Works: Arithmetic Logic Unit from Gates.

Use case 3: sorting networks

A sorting network is a fixed-topology circuit that sorts N inputs in parallel. Its building block is the compare-and-swap cell: two inputs in, two outputs out, with the smaller value forced to the lower output. Implementation is a magnitude comparator driving a pair of 2-to-1 multiplexers — the comparator decides which input is larger, and the multiplexers route them accordingly.

A bitonic sorter on 16 values uses 80 such cells. A Batcher odd-even mergesort on the same 16 uses 63. Both rely entirely on magnitude comparators for the decision logic; the rest is wiring and multiplexers.

A worked example: comparing 0110 and 0101

Take A = 0110 (6) and B = 0101 (5).

1. Bit-3: A3 = 0, B3 = 0 — tied. $E_3 = 1$, $G_3 = 0$, $L_3 = 0$.
2. Bit-2: A2 = 1, B2 = 1 — tied. $E_2 = 1$, $G_2 = 0$, $L_2 = 0$.
3. Bit-1: A1 = 1, B1 = 0 — A wins here. $E_1 = 0$, $G_1 = 1$, $L_1 = 0$.
4. Bit-0: A0 = 0, B0 = 1 — does not matter, the verdict is already in.

Plugging into the chained equations:

$G = G_3 + E_3 G_2 + E_3 E_2 G_1 + E_3 E_2 E_1 G_0 = 0 + 0 + 1 \cdot 1 \cdot 1 + \text{don't care} = 1$

$E = E_3 E_2 E_1 E_0 = 1 \cdot 1 \cdot 0 \cdot \text{anything} = 0$

$L = L_3 + E_3 L_2 + E_3 E_2 L_1 + E_3 E_2 E_1 L_0 = 0$

Output: A > B, as expected.

Build it and watch the verdict shift

Open the /docs/COMPARATOR block, drive the two inputs with toggle switches, and step through cases. Move both inputs to the same value and the equality output goes high; raise the MSB on one side and that side’s greater-than output snaps high regardless of the lower bits. The next step is the ALU — open the 4-Bit ALU Demonstration and watch the comparison flags appear as part of the broader status register, alongside Carry, Zero, Negative, and Overflow.