Binary Number Analyzer Circuit Simulator

Le simulateur interactif nécessite JavaScript

Active JavaScript pour charger le circuit en direct. La table de vérité ci-dessous décrit le comportement du circuit.

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Ce que tu apprendras

Compute the zero-detect signal as inverted OR-reduce of all input bits.
Compute parity using XOR-reduce of all input bits.
Display the binary value's decimal equivalent on a digit display.
Run multiple bitwise reductions in parallel on the same input bus.
Connect these reductions to CPU status flags (Z, P, S).

Comment ça fonctionne

A binary number analyzer combines several common combinational circuits into one demo: detection of zero, even/odd parity, and value comparison. Each is built from primitive gates and runs in parallel on the same input bus.

- Zero detection: OR-reduce all input bits, then invert. Output high only when every input bit is 0. - Parity (even): XOR-reduce all input bits. Output high when there's an even number of 1s. (XOR-reduce + invert gives even parity; raw XOR-reduce gives odd parity.) - Magnitude indicator: Display the binary value on a digit display, often with a comparator against a threshold.

These three are the fundamental "properties" of a binary number you read directly from its bits without converting to decimal: is it zero? is it odd? how big is it? Real CPUs maintain status flags for exactly these properties (Z, P, S, N) updated every arithmetic operation.

Combining them into one demo highlights how multiple bitwise reductions on the same bus run independently and in parallel — they don't share intermediate signals, just the input bits.

Table de vérité

Selected 4-bit input rows showing zero detection and parity.

Entrées				Sortie
B3	B2	B1	B0	Zero	EvenParity	Decimal
0	0	0	0	1	1	0	0 — Zero=1, even parity (0 ones)
0	0	0	1	0	0	1	1 — odd parity (1 one)
0	1	0	1	0	1	5	5 — even parity (2 ones)
1	1	1	1	0	1	15	15 — even parity (4 ones)

Expression booléenne

\text{Zero} = \overline{B_3 + B_2 + B_1 + B_0}

Inverted OR-reduce: high only when every bit is 0.

\text{Parity}_{\text{even}} = \overline{B_3 \oplus B_2 \oplus B_1 \oplus B_0}

Inverted XOR-reduce: high when there's an even number of 1s.

Essaie étape par étape

Règle les entrées dans la simulation ci-dessus, lis ce qui devrait se produire et vérifie-le.

1

B = 0000

Attendu: Zero=1, Parity=1, Decimal=0

Ce que tu verras: All zeros: Zero detect fires; even parity (0 is even).
2

B = 0011

Attendu: Zero=0, Parity=1, Decimal=3

Ce que tu verras: Two 1s — even parity. Decimal display reads 3.
3

B = 0001

Attendu: Zero=0, Parity=0, Decimal=1

Ce que tu verras: One 1 — odd parity (so even-parity light is off). Decimal reads 1.
4

B = 1111

Attendu: Zero=0, Parity=1, Decimal=15

Ce que tu verras: Four 1s — even parity. Maximum 4-bit value (15) on the display.

Composants utilisés

Applications concrètes

CPU status flags. Every ALU operation updates Zero, Parity, Sign, and other flags. These are wired to the same parallel reductions this circuit demonstrates.

Conditional branch instructions. "Jump if zero" reads the Zero flag — set by the Zero-detect logic on the last ALU result.

Network checksums. Parity bits and CRCs use XOR reductions over packet bytes for error detection.

Interrupt-state polling. A polling controller checks several status registers' parity or zero state to determine if any interrupt is pending.

Memory comparators. Equality compare against a fixed value uses XOR-reduction patterns similar to parity but per-bit XOR with the constant.

Questions fréquentes

Why is zero detection useful?

Many algorithms branch on whether a value is zero — loop termination, null pointer checks, conditional jumps. CPUs maintain a Z flag updated by every ALU operation specifically for this.

What's the difference between even and odd parity?

Even parity means the count of 1s is even (including zero); odd parity means the count is odd. Networks use parity bits to make the total count even (or odd) — flips during transmission can then be detected.

How does parity scale with bit width?

Parity over N bits is just XOR of all N. As tree depth, that's ⌈log₂ N⌉ XOR levels. For 64-bit parity, only 6 XOR delays — very fast.

Can these reductions detect more than single-bit errors?

Single-bit parity catches odd-error counts but is blind to even errors. Hamming codes use multiple parity bits arranged so any single-bit flip uniquely identifies the affected bit. CRCs use polynomial XOR for stronger multi-bit detection.

Why combine them into one circuit?

Educational demonstration of parallel bitwise reductions. In real CPUs the Zero, Sign, Parity, and Carry flags are all computed in parallel from the same ALU result — exactly the pattern this circuit shows.