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Magnetic-Core Memory Plane

Computing · c. 1953

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Magnetic-Core Memory Plane

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ADDRESSX3 · Y4

ADDRESS MATRIX

click a cell to address it · X = column, Y = row

LOAD MEMORY

Reading the plane

stored 1 · +Br ↻
stored 0 · −Br ↺
half-select · holds

MEMORY BUSIDLE

ADDRESSX3 · Y4011 · 100DATA—OPERATIONIDLELAST SENSE—

X3Y4INHIBITSENSE

SENSE AMPLIFIER

HYSTERESIS LOOPB vs H

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c. 1953 · Computing

Magnetic-Core Memory Plane

An 8 × 8 teaching plane demonstrates coincident-current selection, destructive readout, and write-back.

Magnetic-core memory stores a bit as one of two remanent magnetization states of a ferrite toroid. Coincident-current addressing sends partial selection currents through one X line and one Y line so their combined field can switch the core at the crossing while half-selected neighbors remain below the intended switching threshold.

This exhibit is an 8 × 8 instructional plane. Each cell stores a software state and follows a prescribed threshold-and-hysteresis display model. A modeled read drives the selected cell toward zero; a previous one produces a displayed sense pulse, followed by restoration. The inhibit line demonstrates how a write cycle can leave the cell at zero. The B–H loop, current arrows, and sense waveform are qualitative visualizations, not electromagnetic field or induced-voltage calculations.

Coincident-current magnetic-core memory was developed around MIT’s Whirlwind program and entered operation there during the early 1950s before becoming an important memory technology. Implementations varied, and core memory did not equip every computer. Its destructive read-and-restore cycle is historically significant but should not be described as the ancestor of every modern RAM access protocol.

Specifications

Exhibit scale: 8 × 8 software-state memory plane
Addressing: Modeled coincident X/Y partial currents and threshold
Sequence: Destructive read, displayed sense pulse, and write-back
Scope: Qualitative hysteresis display; no electromagnetic field solve

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