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Hardware, not instructions.
Follow the same inputs into independent logic cells.
3D view focused · A–D inputs · Space clock · R reset · L labels · 1–6 chapters · Esc to release
3D rendering is unavailable
The logic controls, truth tables and waveform engine remain available.
Start with a five-minute experiment
In Full adder, toggle A, B and C. SUM is their parity; CARRY is high when at least two are high. No clock is needed. Open Inside a LUT to see which stored bit the inputs select. Change a memory bit: you have reconfigured a circuit, not changed a data input.
Next load the 2-stage pipeline, open Remember a bit, and pulse the clock. Both registers sample their D values on the same edge. The second register samples the previous first-register output—not a value just produced by that edge. Turn CE off to hold state. SRST is synchronous and takes priority over CE.
What a LUT actually means
For a four-input LUT, the address is I0 + 2·I1 + 4·I2 + 8·I3. There are 16 stored bits. INIT[address] is the combinational result. The visible 16→8→4→2→1 tree is a logically equivalent network of 15 two-input multiplexers. I0 selects within pairs; I1, I2 and I3 select progressively larger groups. This explanation does not assert a specific transistor layout. The tree displays the selection implied by the arrived LUT inputs; its internal gates are not individually delay-simulated. F updates after one aggregate 620 ps LUT delay.
For example, 0x6666 implements I0 XOR I1; 0x9696 implements three-input parity; 0xE8E8 implements a three-input majority function. The upper eight entries repeat when a function ignores I3. LUT memory contents stay unchanged while data inputs vary.
What is configurable—and what is not?
Configuration determines LUT bits, input sources and whether a cell’s exposed output uses F or registered Q. The muxes and metal wiring already exist in the manufactured chip; configuration selects their behavior. The routing microscope abstracts this as one selected source per destination. Real devices have finite, family-specific tracks, switch connectivity and routing constraints, not a universal crossbar.
The lab’s 16 cells each have one LUT4 and one optional positive-edge DFF. A real configurable logic block usually groups multiple logic elements; the names, LUT sizes, packing and sharing rules vary by family. Some FPGAs use larger or fracturable LUTs. FPGA configuration technologies also vary: do not infer that every FPGA uses volatile SRAM configuration.
The digital engine
The engine uses integer picoseconds, queued signal events, transport delays on interconnect and an inertial LUT delay. Nonconstant route delay is 260 ps + 140 ps × Manhattan hops + added route delay. Tied constants have zero modeled route delay. LUT delay is 620 ps; clock-to-Q is 220 ps; setup and hold are 200 ps and 120 ps. These are explanatory numbers, not specifications for any chip.
All D inputs are sampled before any Q changes at a shared ideal rising edge. Counter feedback is therefore synchronous. All-combinational feedback loops are rejected. X means a digital value is not guaranteed: an unknown LUT input yields a known result only when all matching table entries agree. A setup/hold violation produces a conservative unknown state. The engine does not predict an analog metastability voltage or its probabilistic resolution.
Clock pulse schedules one complete pulse at a future 12 ns clock-grid boundary after the current state has had setup time. Idle boundaries can be skipped between user actions; this is an interactive testbench, not a continuously running oscillator. Run clock repeatedly queues such pulses. Next event pauses automatic propagation and advances one simulation timestamp. The waveform instrument and VCD export contain actual recorded model states, not illustrative sine waves. The display keeps a rolling history of up to 4,000 event-time snapshots.
Timing is an explicit, separate worksheet
The timing chapter does not change the live circuit or its waveform. It checks a hypothetical register-to-register path at illustrative min/max corners. Setup uses the latest arrival: tCQ(max) + route(max) + N·tLUT(max). Its deadline is T + capture−launch skew − uncertainty − setup. Hold uses earliest arrival and requires it to exceed capture−launch skew + uncertainty + hold. Positive capture skew helps setup and hurts hold. Reducing clock frequency alone does not fix a same-edge hold violation.
The worksheet uses tCQ max/min = 0.22/0.10 ns and tLUT max/min = 0.62/0.18 ns. A conservative 0.10 ns uncertainty allowance is applied separately to each check. A reported setup-only frequency bound is not a whole-design timing guarantee. The worksheet omits clock reconvergence, exceptions, multi-cycle paths, multi-clock analysis and vendor timing corners.
Configuration and the small compiler
The Boolean mapper accepts at most four variables plus NOT, AND, XOR, OR and parentheses. It parses an expression, evaluates all 16 cases, and exactly maps that function into one LUT4. It assigns a fixed teaching cell and four input connections. It does not synthesize arbitrary Verilog, solve real routing congestion, run timing-driven placement, or generate a vendor bitstream. The generated RTL describes the current configured lab netlist, including synchronous reset and nonblocking register assignments. FPGA register initialization support is target/tool dependent.
Programming a word, changing a route or selecting registered/bypass output is treated as a whole-model reconfiguration: the clock stops, runtime and waveform history restart, Q initializes to 0, and the chosen primary input levels are retained. This is not a simulation of live partial reconfiguration. JSON project files store the circuit and primary inputs, not the analog or transient runtime state.
Hard resources and model limits
The BRAM and DSP columns are architectural context; they are inspectable but not instantiated in the supplied logic netlists. Dedicated carry chains accelerate arithmetic in many real architectures. The adder and counter here intentionally use LUT logic to expose the Boolean mechanism; they do not claim an optimized carry-chain mapping.
No transistor behavior, power, heat, signal integrity, analog metastability, electrical I/O standards, detailed clock-tree skew, SRAM upset probability, device speed grade or manufacturer pinout is modeled. Cross-layer spacing, package-like pads and dimensions are illustrative. Running this JavaScript simulator is not running an FPGA: it reproduces the stated digital semantics in software.
Controls and accessibility
Drag to orbit, Shift-drag or right-drag to pan, pinch to zoom. Select Top for an orthographic plan view. Click a logic cell, a LUT bit or a routing crosspoint. All editable circuit parameters are also available in normal form controls. While the 3D view has focus, scrolling zooms, arrow keys orbit, A–D toggle primary inputs, Space queues a clock pulse, R resets the runtime, 1–6 change chapters, L toggles labels, ? opens this guide and Escape releases the view. The lab uses native WebGL 2 and computes every signal in this browser.
Primary technical references
Architectural concepts and timing equations were checked against the following sources. External links open in a new tab.
Why dedicated memory exists
A LUT stores a small truth table, and some FPGA LUTs can also be configured as distributed memory. Larger buffers, FIFOs and tables are more efficiently implemented using dedicated block RAM resources. Real blocks have specific capacities, widths, port modes, write enables, read timing and read-during-write behavior.
A different role for bits
In this lab a LUT’s INIT bits define a Boolean function. In a running memory design, addresses, data and write enables access user data. These two uses must not be confused with the configuration bits that choose the RAM’s operating mode or route its ports.
Select the amber LUT cells to return to the simulated datapath. No BRAM latency, dual-port collision behavior or stored user data is fabricated by this visual model.
A multiplier does not have to consume many LUTs
Many FPGA families include dedicated arithmetic blocks for operations such as multiplication and multiply-accumulate. They can include pipeline registers, adders, operand muxes and cascade connections. Width, signedness, supported operations and timing are device-specific.
From HDL to the right resource
A synthesis tool may infer a DSP block from arithmetic RTL when the target, operand widths and synthesis settings permit it. It may instead implement a smaller function in LUTs. More hardware resources can operate concurrently; their throughput and latency still depend on clocking, pipelining and data movement.
This learning lab deliberately exposes small LUT-based functions. It does not claim that its schematic DSP column is a simulated vendor arithmetic primitive.
Save your configured LUT words, routes, register selections and primary input levels. Waveforms and transient register state are not part of a configuration file.
Portable configuration
A readable, validated JSON file in the FABRIC format. Not a vendor bitstream.
Browser-local checkpoint
Stored only in this browser. Availability depends on the browser’s storage policy.
Recorded signal activity
Export the current event-time trace in standard Value Change Dump format (1 ps timescale).
Readable hardware description
Generated from the actual programmed netlist, not an uncommitted expression draft.
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