Logic Lab reference
Every documented component, with its simulator representation in view.
61 components across 10 families. Search by name, symbol or what you are trying to build.
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61 components
Input/Output
7 components
Input SwitchUse the Input Switch as a manual one-bit source in DigiSim Logic Lab. Each click changes its driven output between LOW (0) and HIGH (1) for controlled circuit experiments.
ClockUse DigiSim's Clock as a periodic digital source for sequential circuits. It produces a 50% duty-cycle LOW/HIGH waveform at a configurable 0.1–20 Hz simulation frequency.
ConstantUse the Constant component as a fixed, actively driven HIGH (1) source in DigiSim Logic Lab. It is a logical source rather than a modeled supply rail or pull-up resistor.
Constant ZeroUse Constant Zero as a fixed, actively driven LOW (0) source in DigiSim Logic Lab. It represents a logic value, not an electrical ground or pull-down resistor model.
Output LightUse the one-input Output Light to inspect a digital node. The visual indicator is on for HIGH and off for LOW without loading or driving the simulated circuit.
Digit DisplayUse the four-input Digit Display to render one hexadecimal character, 0–F. The component interprets A0–A3 as an unsigned nibble, with A0 as the least-significant bit.
7-Segment Display (8-Pin)Drive the Seven-Segment Display through active-HIGH inputs a–g and DP. Each input controls one visual segment, so the component can show digits or custom patterns.Logic Gates
10 components
AND GateThe two-input AND gate implements Boolean conjunction: its output is HIGH only when both sampled inputs are HIGH. Use it to combine simultaneous logic conditions.
OR GateThe two-input OR gate implements inclusive Boolean OR: its output is HIGH when either or both sampled inputs are HIGH, and LOW only when both are LOW.
NOT GateThe one-input NOT gate implements Boolean complementation, driving HIGH for a sampled LOW input and LOW for a sampled HIGH input.
BufferDigiSim's one-input Buffer reproduces the sampled logic value as a driven output. Its functional model does not calculate electrical drive strength, current, loading, or edge rate.
NAND GateThe two-input NAND gate implements the complement of AND. NAND is functionally complete, so any Boolean function can be expressed using NAND gates alone.
NOR GateThe two-input NOR gate implements the complement of OR. NOR is functionally complete and can also form an active-HIGH SR latch through cross-coupled feedback.
XOR GateThe two-input XOR gate outputs HIGH when its sampled inputs differ. It is the sum function of a half adder and a building block for parity and controlled inversion.
XNOR GateThe two-input XNOR gate is the complement of XOR and outputs HIGH when its sampled inputs are equal. Combine bitwise XNOR results with AND for word equality.
Tri-State BufferUse DigiSim's active-HIGH Tri-State Buffer to drive LOW or HIGH when enabled and release its output to high impedance (Z) when disabled.
8-Bit Tri-State BufferUse the active-HIGH 8-bit Tri-State Buffer to gate D0–D7 onto Y0–Y7 as a group. Disabling EN releases all eight outputs to Z for bus sharing.Multiplexers/Demultiplexers
6 components
Multiplexer (2-to-1)Use the combinational 2-to-1 Multiplexer to route I0 or I1 to Y. Select S=0 chooses I0; S=1 chooses I1.
Multiplexer (4-to-1)Use the combinational 4-to-1 Multiplexer to route one of I0–I3 to a single output. S1S0 selects inputs 00 through 11 respectively.
Multiplexer (8-to-1)Use the combinational 8-to-1 Multiplexer to route one of I0–I7 to its output. Three select inputs encode the selected input index.
Demultiplexer (1-to-2)Use the combinational 1-to-2 Demultiplexer to route input D to Y0 when S=0 or Y1 when S=1 while driving the unselected output LOW.
Demultiplexer (1-to-4)Use the 1-to-4 Demultiplexer to route D to one of Y0–Y3. Two select inputs choose the destination; every unselected output remains LOW.
Demultiplexer (1-to-8)Use the 1-to-8 Demultiplexer to route D to one of Y0–Y7. Three select inputs choose the destination while all unselected outputs remain LOW.Encoders/Decoders
5 components
Encoder (4-to-2)Use DigiSim's 4-to-2 Priority Encoder to encode the highest-numbered active input as a two-bit value. Input 3 has the highest priority.
Encoder (8-to-3)Use DigiSim's 8-to-3 Priority Encoder to encode the highest-numbered active input as a three-bit value. Input 7 has the highest priority.
Decoder (2-to-4)Use the combinational 2-to-4 Decoder to convert a two-bit unsigned input into four active-HIGH one-hot outputs.
Decoder (3-to-8)Use the combinational 3-to-8 Decoder to convert a three-bit unsigned input into eight active-HIGH one-hot outputs for selection logic.
BCD-to-7-Segment DecoderUse DigiSim's combinational BCD-to-7-Segment Decoder to map A0–A3 into active-HIGH segment outputs a–g. Decimal inputs 0–9 display digits; inputs 10–15 are blanked.Arithmetic
8 components
Half AdderUse the combinational Half Adder to add one-bit inputs A and B. Sum is A XOR B, and Carry is A AND B; there is no carry-in input.
Full AdderUse the combinational Full Adder to add A, B, and Cin, producing a one-bit Sum and Cout. Cascading Cout into the next stage's Cin forms a wider adder.
Adder (4-bit)Use DigiSim's combinational 4-bit Adder to compute A[3:0] + B[3:0] + Cin. It outputs the low four sum bits and unsigned Cout as one functional component.
Adder (8-bit)Use DigiSim's combinational 8-bit Adder to compute A[7:0] + B[7:0] + Cin. It outputs the low eight sum bits and unsigned Cout as one functional component.
Comparator (4-bit)Use the combinational 4-bit Magnitude Comparator to compare A[3:0] and B[3:0] as unsigned values. Exactly one of A>B, A=B, and A<B is HIGH for defined inputs.
Comparator (8-bit)Use the combinational 8-bit Magnitude Comparator to compare two bytes as unsigned values. It drives mutually exclusive A>B, A=B, and A<B outputs.
ALU (4-bit)Use DigiSim's combinational 4-bit ALU for ADD, SUB, AND, OR, XOR, NOT A, SHL A, and logical SHR A. It drives R0–R3 plus Zero, Carry, Negative, and Overflow.
ALU (8-bit)Use DigiSim's combinational 8-bit ALU for ADD, SUB, AND, OR, XOR, NOT A, SHL A, and logical SHR A, with active-HIGH OE and four status outputs.Memory
9 components
SR LatchUse DigiSim's active-HIGH SR Latch to store one bit. S=1,R=0 sets Q; S=0,R=1 resets Q; S=R=0 holds; S=R=1 produces driven unknown outputs.
D LatchUse DigiSim's active-HIGH D Latch as a level-sensitive one-bit store. Q and Q-bar follow D while EN=1 and retain the last captured state while EN=0; there is no clock or reset input.
D Flip-FlopUse DigiSim's positive-edge D Flip-Flop to capture D and drive Q/Q-bar. Active-HIGH asynchronous PRE and CLR override the clock, with CLR taking priority if both are HIGH.
JK Flip-FlopUse DigiSim's positive-edge JK Flip-Flop for hold, set, reset, and toggle behavior. Active-HIGH asynchronous PRE and CLR are provided, with CLR taking priority.
T Flip-FlopUse DigiSim's positive-edge T Flip-Flop to hold when T=0 and toggle when T=1. Its active-HIGH asynchronous CLR forces Q LOW and Q-bar HIGH.
Register (4-bit)Use DigiSim's 4-bit Register to capture D0–D3 on a rising CLK edge when LD=1. Active-HIGH CLR clears asynchronously; Q0–Q3 are always driven.
Register (8-bit)Use DigiSim's 8-bit Register to capture D0–D7 on a rising CLK edge when LD=1. CLR is asynchronous and active HIGH; OE controls tri-state Q0–Q7.
Shift Register (4-bit)Use DigiSim's 4-bit Shift Register for rising-edge parallel load or bidirectional serial shift. S/L=1 loads D0–D3; S/L=0 shifts according to DIR.
Shift Register (8-bit)Use DigiSim's 8-bit Shift Register for rising-edge parallel load or bidirectional serial shift. S/L=1 loads D0–D7; S/L=0 shifts according to DIR.Counters
3 components
Counter (4-bit)Use DigiSim's fixed 4-bit binary up-counter for modulo-16 counting. It increments on a rising CLK edge when EN=1 and clears asynchronously when CLR=1.
Counter (8-bit)Use DigiSim's fixed 8-bit up-counter for modulo-256 counting. It increments on rising CLK when EN=1, clears asynchronously when CLR=1, and treats LD as reserved.
Program Counter (8-bit)Use DigiSim's 8-bit Program Counter to hold, increment, or synchronously load an address. RST is asynchronous; OE controls the tri-state A0–A7 outputs.CPU & Advanced
9 components
Instruction RegisterUse DigiSim's 8-bit Instruction Register to capture I0–I7 on a rising CLK edge when LD=1. Its low nibble always drives opcode outputs; A_OE gates the high-nibble address outputs.
Control UnitUse DigiSim's fixed 8-bit CPU Control Unit to decode a low-nibble opcode and issue datapath controls across FETCH, DECODE, EXECUTE, and STORE states.
Assembly Program LoaderUse the Assembly Program Loader to assemble its supported one-byte instruction syntax and transfer the resulting bytes into RAM through explicit address, data, and control pins.
Flags RegisterUse DigiSim's Flags Register to capture Z, C, N, and V inputs on a rising CLK edge when LD=1. Active-HIGH CLR clears all four stored outputs asynchronously.
AccumulatorUse DigiSim's 8-bit Accumulator as a clocked byte register with active-HIGH LD, asynchronous CLR, and tri-state outputs controlled by active-HIGH OE.
RAMUse DigiSim's fixed 256 × 8 RAM with rising-edge synchronous writes, asynchronous reads, and tri-state Q0–Q7. CS, WE, and OE are active HIGH.
ROMUse DigiSim's fixed 256 × 8 ROM as an asynchronous, tri-state program or lookup memory. CS and OE are active LOW, and the circuit has no run-time write interface.
Memory Address Register (MAR)Use DigiSim's 8-bit Memory Address Register to capture D0–D7 on a rising CLK edge when LD=1 and continuously drive the stored value on A0–A7.
8-Bit Data BusUse DigiSim's 8-bit Data Bus block to mirror eight resolved bus inputs D0–D7 to Q0–Q7 while preserving LOW, HIGH, unknown X, and released Z per bit.Visualization
3 components
Pixel Screen (16x16)Use the pinless 16×16 monochrome Pixel Screen to visualize a 32-byte framebuffer in workspace RAM. It is a memory-polling display model, not an electrically wired LED matrix.
Oscilloscope (2 Channel)Use DigiSim Logic Lab's 2-channel Oscilloscope to inspect digital LOW, HIGH, X, and Z transitions against simulator time without driving the circuit.
Oscilloscope (8 Channel)Use DigiSim Logic Lab's 8-channel Oscilloscope to inspect eight digital traces, buses, and control sequences with event-timed capture and configurable triggering.