# DigiSim Logic Components

> Comprehensive reference for all digital logic components available in DigiSim, including their behavior, pin configurations, and usage in circuit design.

## Component Library Overview

DigiSim offers 60+ digital logic components organized into categories:
- **Input Components**: Switches, clocks, constants
- **Basic Logic Gates**: AND, OR, NOT, NAND, NOR, XOR, XNOR, Buffer
- **Sequential Logic**: Flip-flops, latches, registers, counters
- **Arithmetic**: Adders, comparators, ALU
- **Data Routing**: Multiplexers, demultiplexers, encoders, decoders
- **Memory**: RAM, ROM
- **Output & Display**: LEDs, 7-segment displays, oscilloscopes, pixel screens
- **CPU Architecture**: Program counter, instruction register, control unit, accumulator

## Input Components

### INPUT_SWITCH
- **Function**: Manual toggle switch for user input
- **Pins**: 1 output
- **Behavior**: Click to toggle between 0 and 1
- **Usage**: Primary input control for circuit testing

### CLOCK
- **Function**: Configurable frequency clock generator
- **Pins**: 1 output
- **Default Frequency**: 1Hz (adjustable)
- **Behavior**: Continuous square wave output
- **Usage**: Synchronous circuit timing, flip-flop clocking

### CONSTANT / CONSTANT_ZERO
- **Function**: Fixed logic values
- **Pins**: 1 output each
- **Values**: CONSTANT (1), CONSTANT_ZERO (0)
- **Usage**: Tie inputs to known states, enable signals

## Basic Logic Gates

### AND Gate
- **Function**: Logical AND operation
- **Pins**: 2-8 inputs, 1 output
- **Truth Table**: Output = 1 only when all inputs = 1
- **Symbol**: D-shaped gate with flat input side

### OR Gate
- **Function**: Logical OR operation
- **Pins**: 2-8 inputs, 1 output
- **Truth Table**: Output = 1 when any input = 1
- **Symbol**: Curved input side gate

### NOT Gate (Inverter)
- **Function**: Logical inversion
- **Pins**: 1 input, 1 output
- **Truth Table**: Output = opposite of input
- **Symbol**: Triangle with circle (bubble)

### NAND Gate
- **Function**: Inverted AND operation
- **Pins**: 2-8 inputs, 1 output
- **Truth Table**: Output = 0 only when all inputs = 1
- **Symbol**: AND gate with output bubble

### NOR Gate
- **Function**: Inverted OR operation
- **Pins**: 2-8 inputs, 1 output
- **Truth Table**: Output = 0 when any input = 1
- **Symbol**: OR gate with output bubble

### XOR Gate
- **Function**: Exclusive OR operation
- **Pins**: 2-8 inputs, 1 output
- **Truth Table**: Output = 1 when odd number of inputs = 1
- **Symbol**: OR gate with curved input line

### XNOR Gate
- **Function**: Inverted exclusive OR
- **Pins**: 2-8 inputs, 1 output
- **Truth Table**: Output = 1 when even number of inputs = 1
- **Symbol**: XOR gate with output bubble

### BUFFER
- **Function**: Non-inverting amplifier
- **Pins**: 1 input, 1 output
- **Purpose**: Signal conditioning, drive strength
- **Symbol**: Triangle without bubble

## Sequential Logic Components

### D Flip-Flop
- **Function**: Data storage with clock synchronization
- **Pins**: D (data), CLK (clock), PRE (preset), CLR (clear), Q, Q̅
- **Behavior**: Captures D input on clock rising edge
- **Usage**: Registers, counters, state machines

### JK Flip-Flop
- **Function**: Universal flip-flop with toggle capability
- **Pins**: J, K, CLK, PRE, CLR, Q, Q̅
- **Behavior**: Set (J=1,K=0), Reset (J=0,K=1), Toggle (J=1,K=1)
- **Usage**: Counters, frequency dividers

### T Flip-Flop
- **Function**: Toggle flip-flop for frequency division
- **Pins**: T (toggle), CLK, CLR, Q, Q̅
- **Behavior**: Toggles output when T=1 and clock edge occurs
- **Usage**: Binary counters, frequency division

### SR Latch
- **Function**: Basic memory element
- **Pins**: S (set), R (reset), Q, Q̅
- **Behavior**: Set (S=1), Reset (R=1), Hold (S=0,R=0)
- **Usage**: Basic memory, debouncing circuits

### D Latch
- **Function**: Transparent latch with enable
- **Pins**: D (data), EN (enable), Q, Q̅
- **Behavior**: Transparent when EN=1, holds when EN=0
- **Usage**: Data storage, address latching

## Memory and Storage Components

### REGISTER_8BIT
- **Function**: 8-bit parallel register
- **Pins**: D0-D7 (data), CLK, CLR, Q0-Q7
- **Behavior**: Stores 8-bit data on clock edge
- **Usage**: Data storage, CPU registers

### SHIFT_REGISTER_8BIT
- **Function**: 8-bit shift register with serial I/O
- **Pins**: Serial In, D0-D7, CLK, Mode, CLR, Q0-Q7, Serial Out
- **Modes**: Shift left/right, parallel load
- **Usage**: Serial-to-parallel conversion, delay lines

### COUNTER_8BIT
- **Function**: 8-bit binary counter
- **Pins**: CLK, CLR, EN, LOAD, Q0-Q7, Carry
- **Behavior**: Increments on clock edge when enabled
- **Usage**: Address generation, timing circuits

### RAM
- **Function**: Random access memory
- **Pins**: Address bus, Data bus, WE (write enable), CS (chip select)
- **Behavior**: Read/write data at specified addresses
- **Usage**: Data storage, program memory

### ROM
- **Function**: Read-only memory
- **Pins**: Address bus, Data bus, CS (chip select)
- **Behavior**: Outputs pre-programmed data
- **Usage**: Program storage, lookup tables

## Arithmetic Components

### ALU_8BIT
- **Function**: 8-bit arithmetic logic unit
- **Pins**: A0-A7, B0-B7 (operands), Op0-Op2 (operation), R0-R7 (result), flags
- **Operations**: ADD, SUB, AND, OR, XOR, NOT, shift operations
- **Flags**: Zero, Carry, Negative, Overflow
- **Usage**: CPU arithmetic operations

### HALF_ADDER
- **Function**: Single-bit addition without carry input
- **Pins**: A, B inputs, Sum, Carry outputs
- **Behavior**: Sum = A ⊕ B, Carry = A ∧ B
- **Usage**: Basic arithmetic building block

### FULL_ADDER
- **Function**: Single-bit addition with carry input
- **Pins**: A, B, Cin inputs, Sum, Cout outputs
- **Behavior**: Full binary addition with carry propagation
- **Usage**: Multi-bit adder construction

### ADDER
- **Function**: Multi-bit binary addition
- **Pins**: A0-A3, B0-B3, Cin, Sum0-Sum3, Cout
- **Behavior**: 4-bit binary addition with carry
- **Usage**: Arithmetic circuits, address calculation

### ADDER_8BIT
- **Function**: 8-bit binary addition
- **Pins**: A0-A7, B0-B7, Cin, Sum0-Sum7, Cout
- **Behavior**: 8-bit binary addition with carry propagation
- **Usage**: CPU arithmetic operations, address calculation

### COMPARATOR
- **Function**: 4-bit magnitude comparison
- **Pins**: A0-A3, B0-B3 inputs, A>B, A=B, A<B outputs
- **Behavior**: Compares two 4-bit binary numbers
- **Usage**: Control logic, sorting circuits

### COMPARATOR_8BIT
- **Function**: 8-bit magnitude comparison
- **Pins**: A0-A7, B0-B7 inputs, A>B, A=B, A<B outputs
- **Behavior**: Compares two 8-bit binary numbers
- **Usage**: CPU operations, data sorting

### TRI_STATE_BUFFER
- **Function**: Tri-state buffer with enable
- **Pins**: Data input, Enable, Output
- **Behavior**: Output = Input when enabled, high-Z when disabled
- **Usage**: Bus interfacing, output control

### TRI_STATE_BUFFER_8BIT
- **Function**: 8-bit tri-state buffer
- **Pins**: 8 data inputs, Enable, 8 outputs
- **Behavior**: 8-bit tri-state buffering
- **Usage**: Bus systems, memory interfacing

### ALU
- **Function**: 4-bit arithmetic logic unit
- **Pins**: A0-A3, B0-B3 (operands), Op0-Op2 (operation), R0-R3 (result), flags
- **Behavior**: Basic arithmetic and logic operations
- **Usage**: Simple CPU designs, arithmetic circuits

### REGISTER
- **Function**: 4-bit parallel register
- **Pins**: D0-D3 (data), CLK, CLR, Q0-Q3
- **Behavior**: Stores 4-bit data on clock edge
- **Usage**: Data storage, simple registers

### SHIFT_REGISTER
- **Function**: 4-bit shift register
- **Pins**: Serial In, D0-D3, CLK, Mode, CLR, Q0-Q3, Serial Out
- **Behavior**: Shift operations with parallel load
- **Usage**: Serial data processing, delay lines

### COUNTER
- **Function**: 4-bit binary counter
- **Pins**: CLK, CLR, EN, LOAD, Q0-Q3, Carry
- **Behavior**: Counts up on clock edges
- **Usage**: Basic counting, timing circuits

## Data Routing Components

### MULTIPLEXER
- **Function**: 2-to-1 data selector
- **Pins**: 2 data inputs, 1 select input, 1 output
- **Behavior**: Routes selected input to output
- **Usage**: Basic data switching

### MULTIPLEXER_4TO1
- **Function**: 4-to-1 data selector
- **Pins**: 4 data inputs, 2 select inputs, 1 output
- **Behavior**: Routes one of four inputs to output
- **Usage**: Data multiplexing, bus switching

### MULTIPLEXER_8TO1
- **Function**: 8-to-1 data selector
- **Pins**: 8 data inputs, 3 select inputs, 1 output
- **Behavior**: Routes one of eight inputs to output
- **Usage**: Complex data routing, memory addressing

### DEMULTIPLEXER
- **Function**: 1-to-2 data distributor
- **Pins**: 1 data input, 1 select input, 2 outputs
- **Behavior**: Routes input to selected output
- **Usage**: Basic data distribution

### DEMULTIPLEXER_1TO4
- **Function**: 1-to-4 data distributor
- **Pins**: 1 data input, 2 select inputs, 4 outputs
- **Behavior**: Routes input to one of four outputs
- **Usage**: Address decoding, data distribution

### DEMULTIPLEXER_1TO8
- **Function**: 1-to-8 data distributor
- **Pins**: 1 data input, 3 select inputs, 8 outputs
- **Behavior**: Routes input to one of eight outputs
- **Usage**: Complex address decoding, memory selection

### ENCODER
- **Function**: 4-to-2 priority encoder
- **Pins**: 4 inputs, 2 binary outputs
- **Behavior**: Encodes highest priority active input
- **Usage**: Basic priority encoding

### ENCODER_8TO3
- **Function**: 8-to-3 priority encoder
- **Pins**: 8 inputs, 3 binary outputs
- **Behavior**: Encodes highest priority of 8 inputs
- **Usage**: Interrupt handling, data compression

### DECODER
- **Function**: 2-to-4 binary decoder
- **Pins**: 2 binary inputs, 4 outputs
- **Behavior**: Activates one output based on input code
- **Usage**: Basic address decoding

### DECODER_3TO8
- **Function**: 3-to-8 binary decoder
- **Pins**: 3 binary inputs, 8 outputs
- **Behavior**: Activates one of eight outputs
- **Usage**: Memory address decoding, device selection

## Output and Display Components

### OUTPUT_LIGHT
- **Function**: Visual logic state indicator
- **Pins**: 1 input
- **Behavior**: Illuminates when input = 1
- **Usage**: Circuit debugging, status indication

### DIGIT_DISPLAY
- **Function**: 7-segment hexadecimal display
- **Pins**: 4 inputs (D0-D3)
- **Behavior**: Shows hex digits 0-F
- **Usage**: Numeric output, debugging

### OSCILLOSCOPE
- **Function**: 2-channel signal analyzer
- **Pins**: 2 signal inputs
- **Behavior**: Real-time waveform display
- **Usage**: Basic timing analysis, signal debugging

### OSCILLOSCOPE_8CH
- **Function**: 8-channel signal analyzer
- **Pins**: 8 signal inputs
- **Behavior**: Advanced real-time waveform display
- **Usage**: Complex timing analysis, multi-signal debugging

### SEVEN_SEGMENT_DISPLAY
- **Function**: 7-segment display for single digit
- **Pins**: 7 segment inputs
- **Behavior**: Displays numeric and some alphabetic characters
- **Usage**: Numeric display, status indication

### PIXEL_SCREEN_16x16
- **Function**: 16x16 pixel display matrix
- **Pins**: Address bus, Data bus, control signals
- **Behavior**: Memory-mapped pixel display
- **Usage**: Graphics output, visual feedback

### TEXT
- **Function**: Text label component
- **Pins**: No electrical connections
- **Behavior**: Static text display
- **Usage**: Circuit documentation, labeling

## CPU Architecture Components

### PROGRAM_COUNTER_8BIT
- **Function**: 8-bit program counter
- **Pins**: CLK, EN, LOAD, CLR, Data inputs, Address outputs
- **Behavior**: Sequential address generation
- **Usage**: Instruction fetch, program execution

### INSTRUCTION_REGISTER
- **Function**: Instruction storage and decode
- **Pins**: Data inputs, CLK, EN, Instruction outputs
- **Behavior**: Captures and holds instructions
- **Usage**: Instruction decode, CPU control

### CONTROL_UNIT
- **Function**: CPU control unit for instruction execution
- **Pins**: Instruction inputs, Control outputs
- **Behavior**: Decodes instructions and generates control signals
- **Usage**: CPU implementation, microprocessor design

### ASSEMBLY_PROGRAM_LOADER
- **Function**: Assembly code compilation and loading
- **Pins**: Control signals, Memory interface
- **Behavior**: Compiles assembly to machine code
- **Usage**: Program development, CPU simulation

### FLAGS_REGISTER
- **Function**: CPU status flags storage
- **Pins**: Flag inputs, Flag outputs
- **Behavior**: Stores arithmetic and logic operation flags
- **Usage**: CPU status tracking, conditional operations

### MEMORY_ADDRESS_REGISTER
- **Function**: Memory address storage for CPU operations
- **Pins**: Address inputs, CLK, EN, Address outputs
- **Behavior**: Captures and holds memory addresses for data access
- **Usage**: Memory addressing in CPU fetch/execute cycles

### DATA_BUS_8BIT
- **Function**: 8-bit bidirectional data bus interface
- **Pins**: Data inputs, Data outputs, Direction control, Enable
- **Behavior**: Manages data transfer between CPU components
- **Usage**: CPU data routing, memory interface

### ACCUMULATOR
- **Function**: Primary register for arithmetic operations
- **Pins**: Data inputs, CLK, EN, CLR, Data outputs
- **Behavior**: Stores operands and results of ALU operations
- **Usage**: CPU arithmetic operations, data accumulation

## Component Design Guidelines

### Pin Naming Conventions
- **Inputs**: Labeled with descriptive names (CLK, EN, D0-D7)
- **Outputs**: Clearly marked (Q, Q̅, Sum, Carry)
- **Control**: Standard control signal names (EN, CLR, PRE)

### Visual Design
- **Consistent Sizing**: Standardized component dimensions
- **Clear Labels**: Readable pin labels and component names
- **Color Coding**: Input pins (blue), Output pins (red), Control (green)

### Electrical Behavior
- **Logic Levels**: Standard 0V (logic 0) and 5V (logic 1)
- **Timing**: Setup and hold times for sequential elements
- **Drive Capability**: Standard fan-out specifications